Phase locked state detecting apparatus and image processing apparatus

ABSTRACT

There is provided a phase locked state detecting apparatus for accurately detecting whether or not a phase locked state is canceled, the phase locked state detecting apparatus includes a comparator  17  for comparing a phase of a processing clock signal Smc generated by a phase locked loop for use in an information processing with a phase of a reference clock signal Src; an edge counter  18  for detecting a change of a frequency of the processing clock signal Smc; and a CPU  19  for judging to based on a phase comparison result whether or not the processing clock signal Smc is in the phase locked state with respect to the reference clock signal Src, and subsequently judging based on a detection result of the frequency change whether or not the phase locked state is canceled.

This is a continuation of application Ser. No. 09/834,883 filed Apr. 16,2001, issued as U.S. Pat. No. 6,661,296 on Dec. 9, 2003; the disclosureof which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a technical field of a phase lockedstate detecting apparatus and an information processing apparatus,particularly to a technical field of a phase locked state detectingapparatus for detecting a phase locked state of a signal which is phasecontrolled by a phase locked loop (PLL) circuit, and an informationprocessing apparatus including the phase locked state detectingapparatus.

2. Description of Related Art

In recent years, an audio system has generally spread in which aninformation reproduction apparatus for reproducing music informationfrom a compact disc (CD) is directly connected to an amplifier foramplifying and outputting the reproduced music information via a serialbus or another bus, and the reproduced music information is outputted tothe outside via the amplifier.

In the amplifier in the audio system constituted as described above, areference clock signal is generated based on time informationtransmitted with the reproduced music information. Then, a processingclock signal for use in a reproduction processing in the amplifier isset to a phase locked state based on the reference clock signal. Thephase locked state means a state in which a phase of the reference clocksignal accurately agrees with a phase of the processing clock signal.The processing clock signal maintaining this state is used to perform anecessary reproduction processing.

Moreover, this constitution accurately matches properties in datatransmission of the information reproduction apparatus to those of theamplifier. For example, it matches properties of time information of theinformation reproduction apparatus to those of the amplifier. Therefore,while the information reproduction apparatus transmits the reproducedmusic information to the amplifier, it can amplify and output thereproduced music information.

In the conventional bus, however, depending on a bus type, when theinformation processing apparatus is newly connected to the bus, or whenthe connected information processing apparatus is disconnected from thebus, there may be cases where an initialization processing oftemporarily initializing the information processing apparatus connectedto the bus, and subsequently setting a new connection. For example, theinitialization processing sets an information processing apparatusnumber for information transmission in the bus, or sets one informationprocessing apparatus to generally control the information processingapparatuses interconnected via the bus with respect to the informationtransmission using the bus.

In this case, depending upon the bus type, the initialization processingincludes an initialization processing requiring a long time for updatingall connections in the information processing apparatuses connected tothe bus (hereinafter referred to as long bus reset). The initializationprocessing also includes a short time initialization processing forperforming the initialization processing similar to that of the long busreset (hereinafter referred to as short bus reset).

On the other hand, the initialization processing is performed for thenew connection of the information processing apparatus, even if thereproduction processing is executed in the amplifier. In this case,there is a problem that the music information being subjected to thereproduction processing is temporarily interrupted.

SUMMARY OF THE INVENTION

The present invention has been developed to solve the aforementionedproblem, and an object thereof is to provide a phase locked statedetecting apparatus for accurately detecting whether or not a phaselocked state is canceled in an information processing apparatusconnected to a bus and for minimizing interruption of an informationprocessing when the aforementioned initialization processing is startedduring execution of the information processing in the informationprocessing apparatus, and an information processing apparatus includingthe phase locked state detecting apparatus.

The above object of the present invention can be achieved by a phaselocked state detecting apparatus in accordance with the presentinvention. The phase locked state detecting apparatus detects a phaselocked state of a processing clock signal generated by a phase lockedloop and used in an information processing. The phase locked statedetecting apparatus includes: a comparing device for comparing a phaseof a reference clock signal as the reference for controlling a phase ofthe processing clock signal by the phase locked loop with a phase of theprocessing clock signal and generating a comparison signal; a detectingdevice for detecting a change of frequency of the processing clocksignal and generating a detecting signal; a first determining device fordetermining on the basis of the comparison signal whether or not theprocessing clock signal is in the phase locked state with respect to thereference clock signal, based on; and a second determining device fordetermining on the basis of the detecting signal whether or not thephase locked state is canceled after the first determining devicedetermines that the processing clock signal is in the phase lockedstate.

According to the phase locked state detecting apparatus of the presentinvention, a result of phase comparison of the reference clock signalwith the phase of the processing clock signal is used to determinewhether or not the processing clock signal is in the phase locked state,and it is subsequently determined in accordance with a change offrequency of the processing clock signal whether or not the phase lockedstate is canceled. Therefore, in accordance with the change of thefrequency (i.e., a frequency which does not follow even a change of thereference clock signal for a remarkably short time and does not quicklyfluctuate) of the processing clock signal generated by a phased lockloop, it is determined whether or not the phase locked state iscanceled. Therefore, even when there is a change of the reference clocksignal for the remarkably short time, it is not determined that thephase locked state is canceled. The processing in which the processingclock signal in the phase locked state is used can be continued.

Moreover, the result of the phase comparison is used to determinedwhether or not the processing clock signal is in the phase locked state,and subsequently it is determined based on the change of the frequencyof the processing clock signal itself whether or not the phase lockedstate of the processing clock signal is canceled. Therefore, it canaccurately be detected whether or not the processing clock signal is inthe phase locked state.

In one aspect of the phase locked state detecting apparatus of thepresent invention, the first determining device determines on the basisof the comparison signal that the processing clock signal is in thephase locked state with respect to the reference clock signal when adifference between the phase of the reference clock signal and the phaseof the processing clock signal continues to be not more than a presetvalue for a preset period, and determines that the processing clocksignal is not in the phase locked state with respect to the referenceclock signal when a state of the difference being not more than thevalue does not continue for the period.

According to this aspect, it can securely be determined whether or notthe processing clock signal is in the phase locked state.

In another aspect of the phase locked state detecting apparatus of thepresent invention, the second determining device determines on the basisof the detecting signal that the processing clock signal is in the phaselocked state with respect to the reference clock signal when the changeof the frequency of the processing clock signal is less than a presetthreshold value, and determines that the processing clock signal is notin the phase locked state with respect to the reference clock signalwhen the change is not less than the threshold value.

According to this aspect, only the processing clock signal can be usedto securely determine whether or not the processing clock signal is inthe phase locked state.

The above object of the present invention can be achieved by aninformation processing apparatus in accordance with the presentinvention. The information processing apparatus includes the phaselocked state detecting apparatus for detecting a phase locked state of aprocessing clock signal generated by a phase locked loop and used in aninformation processing. The phase locked state detecting apparatus isprovided with: a comparing device for comparing a phase of a referenceclock signal as the reference for controlling a phase of the processingclock signal by the phase locked loop with a phase of the processingclock signal and generating a comparison signal; a detecting device fordetecting a change of frequency of the processing clock signal andgenerating a detecting signal; a first determining device fordetermining on the basis of the comparison signal whether or not theprocessing clock signal is in the phase locked state with respect to thereference clock signal, based on; and a second determining device fordetermining on the basis of the detecting signal whether or not thephase locked state is canceled after the first determining devicedetermines that the processing clock signal is in the phase lockedstate. The information processing apparatus is provided with: a phasecomparing device for detecting a phase difference between the referenceclock signal and the processing clock signal and outputting a phasedifference signal, being included in the phase locked loop; a filterdevice for subjecting the outputted phase difference signal to apredetermined filter processing and outputting a filter signal, beingincluded in the phase locked loop; a generating device for generating anoscillation clock signal based on the outputted filter signal, beingincluded in the phase locked loop; a frequency division device fordividing a frequency of the generated oscillation clock signal,generating the processing clock signal and outputting the processingclock signal to the phase locked state detecting apparatus and the phasecomparing device, being included in the phase locked loop; and aprocessing device using the processing clock signal in the phase lockedstate with respect to the reference clock signal to perform aninformation processing based on a result of the determination in thephase locked state detecting apparatus.

Therefore, the processing clock signal which is in the phase lockedstate can be used to accurately perform the necessary informationprocessing.

Moreover, even when the reference clock signal changes only for theremarkably short time, the information processing using the processingclock signal in the phase locked state can be continued.

In one aspect of the information processing apparatus of the presentinvention, the information processing is a reproduction processing ofaudio information inputted from the outside.

According to this aspect, the processing clock signal which is in thephase locked state can be used to accurately perform a necessary audioinformation reproduction processing.

Moreover, even when the reference clock signal changes only for theremarkably short time, the reproduction processing using the processingclock signal in the phase locked state can be continued.

In another aspect of the information processing apparatus of the presentinvention, the first determining device determines on the basis of thecomparison signal that the processing clock signal is in the phaselocked state with respect to the reference clock signal when adifference between the phase of the reference clock signal and the phaseof the processing clock signal continues to be not more than a presetvalue for a preset period, and determines that the processing clocksignal is not in the phase locked state with respect to the referenceclock signal when a state of the difference being not more than thevalue does not continue for the period.

According to this aspect, According to this aspect, it can securely bedetermined whether or not the processing clock signal is in the phaselocked state.

In another aspect of the information processing apparatus of the presentinvention, the second determining device determines on the basis of thedetecting signal that the processing clock signal is in the phase lockedstate with respect to the reference clock signal when the change of thefrequency of the processing clock signal is less than a preset thresholdvalue, and determines that the processing clock signal is not in thephase locked state with respect to the reference clock signal when thechange is not less than the threshold value.

According to this aspect, According to this aspect, only the processingclock signal can be used to securely determine whether or not theprocessing clock signal is in the phase locked state.

The above object of the present invention can be achieved by a phaselocked state detecting method, in accordance with the present invention,for detecting a phase locked state of a processing clock signalgenerated by a phase locked loop and used in an information processing.The phase locked state detecting method includes: a comparing process ofcomparing a phase of a reference clock signal as the reference forcontrolling a phase of the processing clock signal by the phase lockedloop with a phase of the processing clock signal and generating acomparison signal; a detecting process of detecting a change offrequency of the processing clock signal and generating a detectingsignal; a first determining process of determining on the basis of thecomparison signal whether or not the processing clock signal is in thephase locked state with respect to the reference clock signal, based on;and a second determining process of determining on the basis of thedetecting signal whether or not the phase locked state is canceled afterthe first determining device determines that the processing clock signalis in the phase locked state.

According to the phase locked state detecting method of the presentinvention, a result of phase comparison of the reference clock signalwith the phase of the processing clock signal is used to determinewhether or not the processing clock signal is in the phase locked state,and it is subsequently determined in accordance with a change offrequency of the processing clock signal whether or not the phase lockedstate is canceled. Therefore, in accordance with the change of thefrequency (i.e., a frequency which does not follow even a change of thereference clock signal for a remarkably short time and does not quicklyfluctuate) of the processing clock signal generated by a phased lockloop, it is determined whether or not the phase locked state iscanceled. Therefore, even when there is a change of the reference clocksignal for the remarkably short time, it is not determined that thephase locked state is canceled. The processing in which the processingclock signal in the phase locked state is used can be continued.

Moreover, the result of the phase comparison is used to determinedwhether or not the processing clock signal is in the phase locked state,and subsequently it is determined based on the change of the frequencyof the processing clock signal itself whether or not the phase lockedstate of the processing clock signal is canceled. Therefore, it canaccurately be detected whether or not the processing clock signal is inthe phase locked state.

In one aspect of the phase locked state detecting method of the presentinvention, the first determining process determines on the basis of thecomparison signal that the processing clock signal is in the phaselocked state with respect to the reference clock signal when adifference between the phase of the reference clock signal and the phaseof the processing clock signal continues to be not more than a presetvalue for a preset period, and determines that the processing clocksignal is not in the phase locked state with respect to the referenceclock signal when a state of the difference being not more than thevalue does not continue for the period.

According to this aspect, it can securely be determined whether or notthe processing clock signal is in the phase locked state.

In another aspect of the phase locked state detecting method of thepresent invention, the second determining process determines on thebasis of the detecting signal that the processing clock signal is in thephase locked state with respect to the reference clock signal when thechange of the frequency of the processing clock signal is less than apreset threshold value, and determines that the processing clock signalis not in the phase locked state with respect to the reference clocksignal when the change is not less than the threshold value.

According to this aspect, only the processing clock signal can be usedto securely determine whether or not the processing clock signal is inthe phase locked state.

The above object of the present invention can be achieved by aninformation processing method, in accordance with the present invention,including the phase locked state detecting method for detecting a phaselocked state of a processing clock signal generated by a phase lockedloop and used in an information processing. The phase locked statedetecting method includes: a comparing process for comparing a phase ofa reference clock signal as the reference for controlling a phase of theprocessing clock signal by the phase locked loop with a phase of theprocessing clock signal and generating a comparison signal; a detectingprocess for detecting a change of frequency of the processing clocksignal and generating a detecting signal; a first determining processfor determining on the basis of the comparison signal whether or not theprocessing clock signal is in the phase locked state with respect to thereference clock signal, based on; and a second determining process fordetermining on the basis of the detecting signal whether or not thephase locked state is canceled after the first determining processdetermines that the processing clock signal is in the phase lockedstate. The information processing method includes: a phase comparingprocess for detecting a phase difference between the reference clocksignal and the processing clock signal and outputting a phase differencesignal in the phase locked loop; a filter process for subjecting theoutputted phase difference signal to a predetermined filter processingand outputting a filter signal in the phase locked loop; a generatingprocess for generating an oscillation clock signal based on theoutputted filter signal in the phase locked loop; a frequency divisionprocess for dividing a frequency of the generated oscillation clocksignal, generating the processing clock signal and outputting theprocessing clock signal so as to be used for the phase locked statedetecting process and the phase comparing process in the phase lockedloop; and a processing process using the processing clock signal in thephase locked state with respect to the reference clock signal to performan information processing based on a result of the determination of thefirst determining process or the second determining process.

Therefore, the processing clock signal which is in the phase lockedstate can be used to accurately perform the necessary informationprocessing.

Moreover, even when the reference clock signal changes only for theremarkably short time, the information processing using the processingclock signal in the phase locked state can be continued.

In one aspect of the information processing method of the presentinvention, the information processing is a reproduction processing ofaudio information inputted from the outside.

According to this aspect, the processing clock signal which is in thephase locked state can be used to accurately perform a necessary audioinformation reproduction processing.

Moreover, even when the reference clock signal changes only for theremarkably short time, the reproduction processing using the processingclock signal in the phase locked state can be continued.

In another aspect of the information processing method of the presentinvention, the first determining device determines on the basis of thecomparison signal that the processing clock signal is in the phaselocked state with respect to the reference clock signal when adifference between the phase of the reference clock signal and the phaseof the processing clock signal continues to be not more than a presetvalue for a preset period, and determines that the processing clocksignal is not in the phase locked state with respect to the referenceclock signal when a state of the difference being not more than thevalue does not continue for the period.

According to this aspect, it can securely be determined whether or notthe processing clock signal is in the phase locked state.

In another aspect of the information processing method of the presentinvention, the second determining process determines on the basis of thedetecting signal that the processing clock signal is in the phase lockedstate with respect to the reference clock signal when the change of thefrequency of the processing clock signal is less than a preset thresholdvalue, and determines that the processing clock signal is not in thephase locked state with respect to the reference clock signal when thechange is not less than the threshold value.

According to this aspect, According to this aspect, only the processingclock signal can be used to securely determine whether or not theprocessing clock signal is in the phase locked state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram showing an example of electric apparatuses (nodes)serially connected according to IEEE 1394 standard;

FIG. 1B is a diagram showing a loop connection of nodes according toIEEE 1394 standard;

FIG. 2A is a diagram showing another example of electric apparatusesserially connected via a serial bus according to IEEE 1394 standard;

FIG. 2B is a diagram showing a transmission manner on the serial bus;

FIG. 3 is a diagram showing a constitution of an isochronous cycle;

FIG. 4 is a diagram showing a constitution of a CIP header;

FIG. 5 is a diagram showing an actual transmission manner;

FIG. 6 is an explanatory view of information transmission before andafter bus reset;

FIG. 7 is a block diagram showing an outline of a music informationreproduction system according to a preferred embodiment;

FIG. 8 is a block diagram showing a detailed constitution of a lockdetector of the embodiment;

FIG. 9 is a flowchart showing a phase locked state detecting processingaccording to the embodiment; and

FIG. 10 is a flowchart showing the phase locked state detectingprocessing according to a modification.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the present invention will be described withreference to the drawings.

Additionally, the embodiment described below conforms to IEEE 1394standard, formally called “Institute of Electrical and ElectronicEngineers (IEEE) Std. 1394 to 1995, IEEE Standard for a High PerformanceSerial Bus”, which has recently been established as a new standard formutually transmitting information among various electric productsincluding a plurality of information apparatuses, e.g., a personalcomputer, a digital video camera, an mini disk (MD) player, and the likevia a serial bus in real time. In the embodiment, there is provided amusic information reproduction system constituted by connecting aninformation reproduction apparatus (hereinafter referred to as a player)for reproducing music information from information recording media suchas DVD to an amplifier for amplifying the reproduced music informationand outputting the information to the outside. In the embodiment, thepresent invention is applied to the system in which it is detectedwhether or not a processing clock signal used as the reference ofprocessing such as amplification processing in the amplifier is in aphase locked state.

(I) Summary of IEEE 1394 Standard

Before description of the embodiment, information transmission by theserial bus based on the IEEE 1394 standard (hereinafter referred tosimply as a serial bus standard) according to the present invention willgenerally be described.

In the serial bus standard, it is standardized that the plurality ofinformation apparatuses (hereinafter referred to simply as nodes) areconnected to one another via the serial bus, and informationtransmission for a plurality of channels are performed among therespective nodes in a time division manner. In the serial bus standard,it is standardized that the information can be transmitted using 63different channels at maximum in the system connected via the serialbus.

In the serial bus standard, when another information apparatus is newlyconnected to a group of information apparatuses already connected to oneanother via the serial bus (i.e., during bus connection), or when theinformation apparatus is disconnected from the group of informationapparatuses (i.e., during bus release), execution of initialization ofthe serial bus, so-called bus reset is standardized. Required time forthe bus reset is set to 167 μsec in the serial bus standard. Moreover,with the bus reset, the following processing is executed, and a newconnection form (hereinafter referred to as a topology) is constructed.

(1) With occurrence of the bus reset, the node having detected theoccurrence of the bus reset sends a bus reset signal indicating theoccurrence of the bus reset to all nodes connected to one another viathe serial bus including. The node is the one to which the informationapparatus is newly connected or the one which is disconnected.

(2) Subsequently, after the bus reset, tree identification is performedin order to connect the respective nodes on a tree. Moreover, the nodepositioned on the top of the connected tree is recognized as a rootnode.

(3) Subsequently, the recognized root node allows the respective nodesto recognize identification numbers (ID numbers) inherent to therespective nodes so that the respective nodes are identified in a treesystem.

(4) Subsequently, connection states of all the nodes in the formed treeare managed, and an isochronous resource manager (IRM) node is set as anode displayed such that the node can be identified by the other nodes.Concretely, channels for use in the respective nodes, and transmissionoccupying time described later are managed as connection states.

(5) Finally, a bus manager node is set as a node for controllinginformation transmission states of all the nodes.

A new topology after the bus reset is constructed through theaforementioned five stages of processing.

Moreover, to actually transmit the information after the construction ofthe topology, a transmission node which is starting the informationtransmission inquires of the IRM node about the present communicationstate in the other nodes. If the channel and transmission occupying timethe transmission node desires to use are available, the transmissionnode acquires the right to transmit the information and starts theinformation transmission.

Additionally, in the mutually connected serial bus, during theinformation transmission, if the bus reset is occurred due to the busrelease or the bus connection, it is standardized that after the busreset, each node can continuously use the channel and transmissionoccupying time used before the bus reset.

Next, the transmission occupying time will briefly be described.

In the serial bus standard, the information from the respective nodes istransmitted by an information unit which is referred to as anisochronous cycle. The isochronous cycle includes an isochronoustransmission region including information to be transmittedsynchronously with information included in another isochronous cycle,and an asynchronous transmission region including information to betransmitted regardless of and asynchronously with other information.Moreover, the information in the isochronous transmission region isdivided for respective different channels in a time division manner, andthe information which differs with each channel is transmitted.

In this case, it is standardized that in the isochronous transmissionregion, a length of the isochronous transmission region in oneisochronous cycle (its length is standardized to be 125 μsec) isstandardized to be 100 μsec at maximum. Therefore, a total of time oftransmission occupied by the information allotted to each channel in oneisochronous transmission region also needs to be set to 100 μsec orless. The transmission time occupied by one channel in the isochronouscycle corresponds to the aforementioned transmission occupying time.Additionally, the transmission occupying time is referred to as a serialbus use band in some case, and as a serial bus use capacity in othercase. Moreover, when the length of the isochronous transmission regionis less than 100 μsec (including 0) in one isochronous cycle, a regionother than the isochronous transmission region in the isochronous cycleis exclusively used as an asynchronous transmission region.

Next, an actual transmission form in the serial bus standard willgenerally be described with reference to FIGS. 1 to 6.

Additionally, FIG. 1 is a diagram showing one form of the topology inthe serial bus standard, FIG. 2 is a diagram illustrating thetransmission form on the serial bus, FIG. 3 is a diagram showing aconstitution of the isochronous cycle, FIG. 4 is a diagram showing aconstitution of a common isochronous packet (CIP) header, FIG. 5 is adiagram showing the actual transmission form, and FIG. 6 is anexplanatory view of information transmission before and after the busreset.

In the serial bus standard, settings are all automatically performedduring connection of the respective nodes, and further a new node can beconnected without cutting off power supply.

On the other hand, for the information transmission form, high speedtransmission is possible in a range of 100 Mbps to 400 Mbps, and furthervarious types of information can be transmitted by real timetransmission, bi-directional transmission and multi-channeltransmission.

Moreover, for each node connection form, as shown in FIG. 1A, forexample, a personal computer PC is connected as a root node, which isthe one on the top of a tree-like topology as described above, andvarious electric products such as a CD player CP, MD player MP, digitalvideo camera DVC, printer PR, laser disc (LD) player LP, refrigeratorRG, tuner T, speaker SP, amplifier AP, television set TV, video taperecorder VT, rice cooker RC, air conditioner AC and washing machine Ware interconnected via serial buses B. These products can generally becontrolled by the personal computer PC.

In the serial bus standard, the number of electric products(corresponding to the nodes) which can be included in one system(connected system in a tree shape via the serial bus) is 63 at maximum,and further 16 connections at maximum between two nodes can be includedin one system. Additionally, a plurality of nodes ND are prohibited frombeing connected in a loop shape in one system as shown in FIG. 1B by thestandard.

The actual transmission form will next be described in more detail.

First, as shown in FIG. 2A, the digital video camera DVC, video taperecorder VT, personal computer PC and set top box SB for broadcastingreception are connected as the nodes to one another via the serial busB, so that information transmission is performed. Concretely, video datafrom the digital video camera DVC, a predetermined control command fromthe video tape recorder VT, similarly a control command for controllingthe other apparatuses from the personal computer PC, and image data(MPEG data compressed according to a moving picture expert group (MPEG)standard and the like) included in a received broadcasting radio wavefrom the set top box SB are sent onto the serial bus B, respectively.

In this case, as the transmission form of each information sent onto theserial bus B, as shown in a third stage from top of FIG. 2B, theinformation from each node occupies the serial bus B in a time divisionmanner and is transmitted on the serial bus. Moreover, each informationis inserted into an isochronous cycle IC as a synchronous unit having alength of 125 μsec on the serial bus B, and transmitted.

A data structure in the isochronous cycle IC will next be described withreference to FIGS. 3 and 4.

As shown in FIG. 3, the isochronous cycle IC is constituted of: a cyclestart packet CSP; constantly inserted into the top of the isochronouscycle IC, for adjusting a standard time of all nodes; isochronouspackets IP for a plurality of channels; an isochronous transmissionregion ICT constituted by including information synchronous with oneanother in time in the respective isochronous packets IP; and anasynchronous transmission region ACT including asynchronous information(e.g., various control information, and response informationcorresponding to the respective control information).

The cycle start packet CSP is usually outputted from the root node.Therefore, when any bus reset occurs as described above, and the rootnode is set/changed onto another node, the node for outputting the cyclestart packet CSP is also changed.

Moreover, a sub action gap SG as a time gap indicating an end of oneisochronous transmission region ICT or an end of one asynchronoustransmission region ACT is inserted into a last part of each isochronoustransmission region ICT and a last part of the asynchronous transmissionregion ACT. Furthermore, an isochronous gap IG as a time gap indicatingan end of each packet is inserted between the isochronous packets IP andbetween the cycle start packet CSP and the top isochronous packet IP. Inthis case, a length of the sub action gap SG is set to be longer thanthat of the isochronous gap IG.

Moreover, one isochronous packet IP is constituted of: an isochronouspacket (IP) header IPH including information indicating a data amount ineach isochronous packet IP, and information indicating a channel fortransmitting the information in each isochronous packet IP; a CIP headerCIPH described later; and a data region DF including actual imageinformation, or voice information. The data region DF includes aplurality of data blocks. For example, with the voice information, datafor one sample is used as one data block.

On the other hand, as shown in FIG. 4, the CIP header CIPH includes atleast: a node identifier (source ID) SID for identifying the node whichhas sent the isochronous packet IP including the CIP header CIPH; a datablock number DBS indicating the number of data blocks included in thedata region DF; order information (data block counter) DBC continuouslyapplied to data in a plurality of data regions DF sent from one node inorder of sending; a data identifier (format ID) FMT indicating a datatype included in the data region DF; associated information (formatdependent field) FDF as data associated with the data type indicated bythe data identifier FMT (e.g., a sampling frequency in a case in whichthe data identifier FMT indicates audio data); and processing timeinformation SYT indicating a time at which a corresponding processing isstarted after reception of the data included in the data region DF bythe node for receiving the data.

The actual transmission form of each data will next be described withreference to FIG. 5.

Additionally, FIG. 5 shows so-called non-blocking transmission as thetransmission form among the transmission forms defined in the serial busstandard.

Moreover, in FIG. 5, an SYT interval indicates an interval at whichprocessing time information SYT is added to transmission data to betransmitted in a transmission node (transmission data to be included inthe data region DF).

As shown in FIG. 5, when the transmission data to be transmitted isgenerated in a certain transmission node, first the processing timeinformation SYT is applied to the transmission data for eachpredetermined interval (interval between time T2 and T1 in FIG. 5) amongthe generated transmission data.

Moreover, the generated transmission data is sent onto the serial bus B(see FIG. 2B). In this case, the order information DBC havingconsecutive numbers, and processing time information SYT are added tothe CIP header CIPH as shown in FIG. 5.

Subsequently, when a reception node receives the isochronous cycle IC inthis state, the reception node resolves the isochronous cycle IC, thenextracts the transmission data, and starts the processing correspondingto each received transmission data at the time described in theprocessing time information SYT (denoted by “R1”, “R2”, . . . in FIG.5).

In this case, a difference between time (e.g., time T1) at which theprocessing time information SYT is applied to the transmission data witheach index added thereto in the transmission node and time (time R1 inthis case) described in the corresponding processing time informationSYT corresponds to a transmission delay on the serial bus B.

Next, the processing in each node with the occurrence of the bus resetwill generally be described with reference to FIG. 6.

Additionally, FIG. 6 shows a node state before and after the bus reset,and transmission state of the data regarding the node. In FIG. 6, “plugcontrol register (PCR) status” indicates a state of a register disposedfor each node, and the state of the register in which informationtransmission state of the node (concretely, the channel and transmissionoccupying time being used) is described.

First, before the bus reset, the PCR status indicates the nodeinformation transmission state, and the data is normally transmitted. InFIG. 6, data flow and PCR status are both “active” before the bus reset.

Subsequently, when the bus reset occurs, and the node having detectedthe occurrence transmits the bus reset signal to all the other nodes,the aforementioned processes (1) to (5) are executed, and the IRM node,and the like are set.

Subsequently, for one second (referred to as an isochronous resourcedelay period) after the IRM node is set and each node identificationnumber is applied, the node having transmitted the data before the busreset uses the same channel and transmission occupying time as thosebefore the bus reset to continuously transmit the data. In FIG. 6, thedata flow is “active”. In this period, the PCR status is in a standbystate. In FIG. 6, the PCR status is “ready”. Additionally, thetransmission node inquires of the IRM node whether the channel andtransmission occupying time used before the bus reset can continuouslybe used.

Moreover, in the inquiry of the IRM node, when the channel used beforethe bus reset is not used yet and the transmission occupying time canfurther be secured, with an elapse of one second after the bus reset,the node uses the information transmission state before the bus reset asit is to continue transmitting the data. In this case, when one secondelapses after the bus reset, the data flow becomes “active” in FIG. 6.

On the other hand, when the channel used before the bus reset is beingused, or when it is impossible to secure the transmission occupyingtime, with the elapse of one second after the bus reset, the node stopsthe data transmission. In this case, when one second elapses after thebus reset, the data flow becomes “off” in FIG. 6.

As described above, when one second elapses after the bus reset, and thenode can secure the channel used before the bus reset and can furthersecure the transmission occupying time before the bus reset, this nodecan normally resume the information transmission.

Moreover, the other nodes temporarily stop the information transmission,inquire of the IRM node about the described in the IRM node andpresently used channel and transmission occupying time each given time,and restart the information transmission when the channel desired to beused is unused and the transmission occupying time can be secured.

For the bus reset (the long bus reset) shown in FIG. 6, the timenecessary for the reset is set to 167 μsec as described above.

This is standardized in the serial bus standard. The node itself fortransferring the isochronous packet IP cannot detect the occurrence ofthe bus reset. Therefore, the time is determined to be sufficiently longsuch that even the node for transferring the longest isochronous packetIP can detect the bus reset.

However, since the time exceeds a time (125 μsec) corresponding to theisochronous cycle IC, smooth transfer of the isochronous packet IP isinhibited.

That is, when the long bus reset occurs during real-time reproduction,which means that the music information is reproduced and outputted whilebeing received in the amplifier, it is determined in the amplifier thatthe phase locked state of the processing clock signal in the amplifieris canceled. Then, the real-time reproduction is interrupted, andso-called dropout of sound sometimes occurs in the amplifier.

To solve the problem, in a P1394a standard which has recently beenestablished as a new serial bus standard, a new standard for executingthe short bus reset (also referred to as arbitrated bus reset) is addedin which the time necessary for the bus reset is as short as 1.4 μsec.

In the short bus reset, the node requesting for the bus reset performsarbitration (i.e., the node which is to be on a transmission siderequests to obtain rights to use the bus). When the bus use right areacquired, the bus reset with a length of about 1.3 μsec is generated. Inthis case, since the other nodes are in a reception mode, all the nodescan detect the occurrence of even the short-time bus reset.

(II) Embodiment

An embodiment of the present invention executed in conformity with theaforementioned serial bus standard (concretely, the P1394a standard inwhich the short bus reset is standardized) will next be described withreference to FIGS. 7 to 9.

Additionally, FIG. 7 is a block diagram showing an outline constitutionof a music information reproduction system according to the embodiment,FIG. 8 is a block diagram showing a detailed constitution of a lockdetector according to the present invention, and FIG. 9 is a flowchartshowing a phase locked state detecting processing according to thepresent invention.

As shown in FIG. 7, a music information reproduction system S of theembodiment is provided with: a player 20 which reproduces musicinformation recorded in information recording media such as DVD tooutput it to a bus B according to the serial bus standard; the bus B asthe serial bus along which information transmission conforming to theserial bus standard is executed; and an amplifier 1 which providesprocessing such as amplification to the transmitted music informationand outputs it to an external speaker (not shown) as output signal Sout.

Moreover, the amplifier 1 is constituted of a demultiplexer 2, aprocessing time information buffer 3, an audio buffer 4, a standardtimer 5, a time information comparator 6, a lock detector 7, a phasecomparator 8 as a phase comparing device, a loop filter 9 as a filterdevice, a VCO 10 as a generating device, a frequency divider 1 as afrequency division device, a digital/analog (D/A) converter 12 as aprocessing device, and an amplifying section 13 as a processing device.

The phase comparator 8, loop filter 9, VCO 10 and frequency divider 11constitute a phase locked loop (PLL circuit).

An operation will next be described.

First, the player 20 reproduces the music information recorded in theinformation recording medium, forms the isochronous packet IP in whichthe reproduced music information is included in the data region DF, andoutputs the packet to the bus B.

In this case, the processing time information SYT indicating a time atwhich the reproduction processing of the music information is started inthe amplifier 1 is included in the CIP header CIPH in the isochronouspacket IP.

Subsequently, the demultiplexer 2 having received the isochronous packetIP extracts the processing time information SYT from the isochronouspacket IP, generates a time information signal Ssyt including theextracted processing time information SYT, and outputs the signal to theprocessing time information buffer 3.

Parallel to this operation, the demultiplexer 2 extracts the musicinformation from the data region DF in the isochronous packet IP,generates an audio signal Sad including the extracted music information,and outputs the signal to the audio buffer 4.

Subsequently, the processing time information buffer 3 temporarilystores the time information signal Ssyt, and outputs the signal to thetime information comparator 6 at a preset timing.

On the other hand, the standard timer 5 generates a standard time signalSrt including time information as a criterion for controlling the entireoperation of the amplifier 1, and outputs the signal to the timeinformation comparator 6.

Thereby, when the time indicated by the reference time signal Srt agreeswith the time described as the processing time information SYT in thetime information signal syt, the time information comparator 6 generatesa reference clock signal Src having a preset reference frequency andoutputs the signal to the lock detector 7 and phase comparator 8.

Subsequently, the phase comparator 8 compares a phase of the referenceclock signal Src with a phase of a processing clock signal Smc,generates a phase difference signal Scp indicating a difference, andoutputs the signal to the loop filter 9.

Moreover, the loop filter 9 passes only a low frequency component presetin the phase difference signal Scp, generates a control voltage signalSc for voltage-controlling an oscillation frequency of the VCO 10, andoutputs the signal to the VCO 10.

Thereby, the VCO 10 generates an oscillation clock signal Svco having afrequency corresponding to the voltage of the control voltage signal Scand outputs the signal to the frequency divider 11.

Subsequently, the frequency divider 11 divides the frequency of theoscillation clock signal Svco, generates the processing clock signal Smcand outputs the signal to the phase comparator 8, lock detector 7 andD/A converter 12.

On the other hand, the lock detector 7 compares the reference clocksignal Src with the processing clock signal Smc, determines whether theprocessing clock signal Smc is in a phase locked state with respect tothe reference clock signal Src, generates a determination signal Slocand outputs the signal to the D/A converter 12.

On the other hand, the audio buffer 4 temporarily stores an audio signalSad, and outputs the signal to the D/A converter 12 at a preset timing.

Thereby, only when the determination signal Sloc indicates that theprocessing clock signal Smc is in the phase locked state with respect tothe reference clock signal Src, the D/A converter 12 uses the processingclock signal Smc as the reference to convert the audio signal Sad toanalog form, generates an analog audio signal Sada and outputs thesignal to the amplifying section 13.

Subsequently, the amplifying section 13 amplifies the analog audiosignal Sada with a preset amplification ratio, generates the outputsignal Sout and outputs the signal to a speaker (not shown).

Detailed constitution and operation of the lock detector 7 will next bedescribed with reference to FIGS. 8 and 9.

As shown in FIG. 8, the lock detector 7 is constituted of edge detectors15 and 16, a comparator 17 as a comparing device, an edge counter 18 asa detecting device, and a CPU 19 as a first and second determiningdevice.

Outline operations of the respective constituting members will next bedescribed.

First, the edge detector 16 detects a timing of a rising edge in thereference clock signal Src, generates an edge signal Sre and outputs thesignal to the comparator 17.

Parallel to this operation, the edge detector 15 detects the rising edgetiming in the processing clock signal Smc, generates an edge signal Smeand outputs the signal to the comparator 17 and edge counter 18.

Thereby, the edge counter 18 counts an interval of the rising edgetiming of the processing clock signal Smc indicated by the inputted edgesignal Sme, regards the interval as a value indicating the frequency inthe processing clock signal Smc and outputs an interval signal Sct tothe CPU 19.

On the other hand, the comparator 17 counts an interval between therising edge timing of the processing clock signal Smc indicated by theedge signal Sme and the rising edge timing of the reference clock signalSrc indicated by the edge signal Sre, regards the interval as adifference between the phase of the processing clock signal Smc and thephase of the reference clock signal Src and outputs a phase differencesignal Scm to the CPU 19.

Moreover, the CPU 19 follows the following procedure to determinewhether or not the processing clock signal Smc is in the phase lockedstate with respect to the reference clock signal Src, generates thejudgment signal Sloc and outputs the signal to the D/A converter 12.

A phase locked state detecting processing executed in the CPU 19according to the present invention will next be described with referenceto FIG. 9.

In the phase locked state detecting processing, as shown in FIG. 9,first, when the amplifier 1 starts receiving music information (via thebus B) (step S1), it is determined based on the phase difference signalScm from the comparator 17 whether or not a state in which a differencebetween the phase of the processing clock signal Smc and the phase ofthe reference clock signal Src is not more than a preset threshold valuepredetermined by experience continues n times in a repetition period ofdetermination of step S2 (step S2). If the difference is not more thanthe preset threshold value, it can be determined that the phases are inthe phase locked state

Subsequently, when the state does not continue n times (step S2; NO), itis determined that the processing clock signal Smc is not in the phaselocked state with respect to the reference clock signal Src at the startof a music information reproduction processing, and the processing ofstep S2 is performed again.

On the other hand, during repetition of the determination, the phase ofthe processing clock signal Smc starts to agree with the phase of thereference clock signal Src by an action of the phase locked loop. Then,the state in which the difference between the phase of the processingclock signal Smc and the phase of the reference clock signal Src is notmore than the preset threshold value continues n times (step S2; YES).In this case, at the timing it is determined that the processing clocksignal Smc comes into the phase locked state with respect to thereference clock signal Src and an actual reproduction processing isstarted (step S3).

Concretely, in the processing of the step S3, the determination signalSloc indicating the phase locked state is outputted to the D/A converter12, and an analog conversion processing of the audio signal Sad andamplification processing in the amplifying section 13 thereby start.

Additionally, when the processing of the step S3 is executed again afterone cycle of the phase locked state detecting processing shown in FIG.9, the reproduction processing interrupted by the last executedprocessing of the step S5 is resumed.

Subsequently, it is determined based on the interval signal Sct from theedge counter 18 whether or not the change of the frequency of theprocessing clock signal Smc is not less than the preset threshold value(step S4). The preset threshold value is a change threshold value bywhich it can be determined that the phase locked state preset byexperience has been canceled.

Moreover, when the change of the frequency is less than the presetthreshold value (step S4; NO), an operation of continuously outputtingthe determination signal Sloc indicating the phase locked state andperforming the determination of the step S4 again is repeated in thepreset period.

In this case, when the short bus reset occurs during execution of thereproduction processing using the processing clock signal Smc in thephase locked state, the node for transmitting the cycle start packet CSPbefore and after the short bus reset is changed to another node.Concretely, for example, the root node is changed to the amplifier 1from the player 20 because of the short bus reset generated from a statechange of the player 20. Then, the operation of the reference timer 5fluctuates only for a remarkably short time (1.4 μsec). Therefore, evenwhen the reference clock signal Src fluctuates for the remarkably shorttime, the frequency of the processing clock signal Src as the output ofthe phase locked loop does not rapidly change. As a result, even whenthe short bus reset occurs, “NO” state of the determination of the stepS4 continues (i.e., the reproduction processing continues).

On the other hand, when it is determined in step S4 that the frequencychange is not less than the preset threshold value (step S4: YES), thetransmission of the processing time information SYT is interrupted bythe occurrence of the long bus reset. Thereby, it is determined that thegeneration of the standard clock signal Src from the time informationcomparator 6 is temporarily discontinued and the phase locked state iscanceled. Then, the determination signal Sloc for temporarilyinterrupting the reproduction processing is generated and outputted tothe D/A converter 12 (step S5).

Subsequently, it is determined whether or not the reproductionprocessing of the music information in the amplifier 1 is all finished(step S6). When the processing is finished, the phase locked statedetecting processing is finished as it is. When the reproductionprocessing is not all finished (step S6), the flow returns to the stepS1 in order to perform the aforementioned processing with respect to themusic information transmitted via the bus B.

As described above, according to the phase locked state detectingprocessing of the present embodiment, a result of comparison of thephase of the processing clock signal Smc with the phase of the referenceclock signal Src is used to determine whether or not the processingclock signal Smc is in the phase locked state. Subsequently, based onthe change of the frequency (i.e., the frequency which does not followthe change of the reference clock signal Src or does not quicklyfluctuate even if the signal changes only for the remarkably short timeby the generation of the short bus reset) of the processing clock signalSmc itself, it is determined whether or not the phase locked state iscanceled. Therefore, it is not determined by the change of the referenceclock signal Src for the remarkably short time that the phase lockedstate is canceled. The reproduction processing using the processingclock signal Smc in the phase locked state can be continued.Additionally, it can be detected more accurately whether or not theprocessing clock signal Smc is in the phase locked state.

Moreover, when the state in which the difference between the phase ofthe reference clock signal Src and the phase of the processing clocksignal Smc is not more than the preset threshold value is continued ntimes, it is determined that the processing clock signal Smc is in thephase locked state. Additionally, when a state in which the differenceis not more than the preset threshold value continues n times, theprocessing clock signal Smc is determined not to be in the phase lockedstate. Therefore, it can be determined more securely whether or not theprocessing clock signal Smc is in the phase locked state.

Furthermore, when the change of the frequency of the processing clocksignal Smc is less than the preset threshold value, it is determinedthat the signal is in the phase locked state. Additionally, when thechange is not less than the preset threshold value, it is determinedthat the phase locked state is canceled. Therefore, only the processingclock signal Smc can be used to securely determine whether or not thesignal is in the phase locked state.

(III) Modification

A modification of the present invention will next be described withreference to FIG. 10.

Additionally, in a flowchart of the phase locked state detectingprocessing according to the modification shown in FIG. 10, theprocessing similar to the processing shown in the flowchart of FIG. 9 isdenoted with the same step numbers, and detailed description thereof isomitted.

In the aforementioned modification, in the determination of the step S2shown in FIG. 9, when the state in which the difference between thephase of the processing clock signal Smc and the phase of the referenceclock signal Src is not more than the preset threshold value does notcontinue n times (step S2; NO), moreover, in the determination of thestep S4, when the change of the frequency of the processing clock signalSmc is not more than the preset threshold value (step S4; NO), theprocessing of the step S2 or S4 is repeated as it is.

Additionally, as in step S2′ or S4′ in FIG. 10, when the state in whichthe difference between the phase of the processing clock signal Smc andthe phase of the reference clock signal Src is not more than the presetthreshold value does not continue n times (step S2′; NO), it isdetermined that the phase locked state is canceled, and the reproductionprocessing is interrupted (step S5). Furthermore, when the change of thefrequency of the processing clock signal Smc is not more than the presetthreshold value (step S4; NO), it is determined that the phase lockedstate is returned, and the reproduction processing can be resumed (stepS3).

In this constitution, it can securely be detected that the phase lockedstate of the processing clock signal Smc is canceled and that the phaselocked state is returned.

In the aforementioned embodiment and modification, the case in which themusic information transmitted from the player 20 is reproduced/processedin the amplifier 1 has been described. Additionally, the presentinvention can also be applied to the detection of the phase locked statein the reproduction apparatus when image information other than themusic information is transmitted, reproduced and processed.

Moreover, in addition to the reproduction processing of the transmittedinformation, the present invention can be applied to the detection ofthe phase locked state in the recording apparatus when the informationcan be recorded in the information recording medium.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The presentembodiments are therefore to be considered in all respects asillustrative and not restrictive, the scope of the invention beingindicated by the appended claims rather than by the forgoing descriptionand all changes which come within the meaning and range of equivalencyof the claims are therefore intended to be embraces therein.

The entire disclosure of Japanese Patent Application No. 2000-113932filed on Apr. 14, 2000 including the specification, claims, drawings andsummary is incorporated herein by reference in its entirety.

1. A phase locked state detecting apparatus for detecting a phase lockedstate of a processing clock signal with respect to a reference clocksignal, the processing clock signal generated by a phase locked loop andused in an information processing, the reference clock signal being thereference for control by the phase locked loop, the phase locked statedetecting apparatus comprising: a detecting device which detects achange of frequency of the processing clock signal and generates adetecting signal; and a determining device which determines on the basisof the detecting signal whether or not the processing clock signal is inthe phase locked state with respect to the reference clock signal;wherein the detecting device comprises an edge counter which counts aninterval of a rising edge timing of the processing clock signal; and aprocessing unit which regards the interval as a value indicating thefrequency of the processing clock signal to detect the change of thefrequency of the processing clock signal.
 2. The phase locked statedetecting apparatus according to claim 1 wherein the determining devicedetermines on the basis of the detecting signal that the processingclock signal is in the phase locked state with respect to the referenceclock signal when the change of the frequency of the processing clocksignal is less than a preset threshold value, and wherein thedetermining device determines that the processing clock signal is not inthe phase locked state with respect to the reference clock signal whenthe change is not less than the threshold value.